This invention relates to semiconductor memory devices and more particularly to a dynamic decoder for an MOS random access memory.
The most widely used semiconductor memory devices at present are dynamic memories as described in U.S. Pat. No. 3,940,747, issued Feb. 24, 1976 to Kuo and Kitagawa, assigned to Texas Instruments. Higher density versions of these dynamic memory systems are shown in Electronics, May 13, 1976, pp. 81-86 and U.S. Pat. No. 4,081,701 issued Mar. 28, 1978 to White et al assigned to Texas Instruments. These high density devices use one-transistor dynamic memory cells which have the advantage of very small size, and thus low cost. As the density increases from 4K up through 16K, 64K and 256K-bit devices, the spacing between rows (called pitch) becomes much smaller so the amount of room allowed for the row decoder becomes less and the design of the decoder becomes more stringent. Prior decoders for connecting a row address to a one of N address for the array are shown in U.S. Pat. Nos. 4,074,237, 4,061,999, and 4,042,915, for example. The prior decoders have had disadvantages in requiring too much room in layout and placing stringent requirements on the input signals with respect to false excursims of signal before they settle out or with respect to timing.
It is a principal object of this invention to provide a dynamic decoder which does not place stringent requirements on address input signal timing and false levels, and which in layout matches the pitch of rows in a dynamic RAM of high density.